# ChipMATE

ChipMATE is a multi-agent framework for generating Verilog RTL code in which a Verilog-writing agent and a Python reference-model agent cross-verify each other's outputs on random test inputs, needing no golden testbench.

The two agents iteratively refine their implementations through this cross-verification loop until they agree, instead of relying on a pre-written golden testbench for self-correction, which real chip-design workflows rarely have available. Because it needs no golden testbench and no human-written spec annotations, the framework is intended to apply directly to industry settings where only a natural-language specification exists; interface port names and bit widths are instead extracted from a structured specification given up front.

The project is the open-source companion to a research paper and reports Pass@1 and Pass@5 results across several RTL generation benchmarks, comparing its own fine-tuned models against general-purpose models such as GPT and Claude.

It is written in Python; model weights are published separately on Hugging Face.

Website: https://chipmate.picasso-lab.com