# FPGA MicroCNN Accelerator

A complete system-on-chip project implementing a quantized convolutional neural network in custom hardware on a twenty-five-dollar FPGA board, classifying blood-cell images faster than an interpreted Python loop on a laptop CPU.

FPGA MicroCNN Accelerator is an end-to-end system-on-chip that implements a small quantized convolutional neural network, MicroCNN, directly in hardware on a Gowin Tang Nano 20K FPGA, to classify biological images from the BloodMNIST dataset. The repository includes the complete RTL implementation, testbenches and host-side software scripts needed to stream raw image pixels over UART to the board, run the convolution and fully-connected layers entirely in custom hardware, and read back the classification result.

The hardware datapath uses a fully pipelined array of multiply-accumulate units, unified line buffers and a custom finite-state-machine controller with dynamic clock gating to reduce power during idle periods, and quantizes weights to INT8 and biases to INT32 with cascaded scale factors for accuracy. The design reports roughly 60 milliseconds of inference latency at 30 megahertz, faster than an interpreted Python loop benchmark on a modern laptop CPU, and a bundled Jupyter notebook lets the network be retrained and re-quantized for a different classification task.

Website: https://github.com/SweiryDev/MicroCNN-TangNano20k