RgGen
RgGen is a Ruby-based code generator for ASIC, IP and FPGA engineers that turns a human-readable register-map specification into SystemVerilog RTL, a UVM register model, C header files and Markdown documentation.
RgGen generates source code related to control and status registers from a register-map specification written in a human-readable format: a Ruby DSL, YAML, JSON, TOML, a spreadsheet format, or SystemRDL through a plugin. Supported outputs include SystemVerilog or Verilog RTL modules for common bus protocols such as AMBA APB, AMBA AXI4-Lite, Avalon-MM and Wishbone, a UVM register model, C header files, and register-map documentation in Markdown.
A plugin system lets users add their own bit-field types or host bus protocols, and separate plugins add Verilog, VHDL, Veryl and SystemRDL support. A browser-based web UI is available alongside the command-line tool. RgGen installs as a Ruby gem, requires Ruby 3.2 or later, and is also distributed as a Docker image for simplified setup.